The ongoing focus on miniaturisation and the increasing complexity and speed requirements of integrated circuits demand for a continuous higher density integration. To achieve this, there is an ongoing downscaling in the dimensions of the active devices as well as of the structures interconnecting these devices. These interconnect structures can comprise multiple metal levels which are, dependent on the aimed interconnect pattern, either separated one from another by means of interlevel insulating layers or connected one to the other by means of a conductive connection through the insulating layer. Besides this downscaling of the dimensions, additional measures are required to be able to meet the stringent speed specifications, i.e. the signal delay. Conventionally the metal levels are Aluminum layers while the insulating layers are oxide layers. Therefore, in order to reduce the signal delay one can choose a metal layer with a higher conductivity compared to Aluminum and/or choose insulating layers with a lower dielectric constant compared to oxide layers. To meet these objectives Cu-containing metal layers and/or Cu-containing connections are or will be introduced in the near future.
The use of Cu in interconnect structures also has some commonly known disadvantages. At first, Cu can have a high diffusion in the surrounding insulating layers which negatively affects the reliability and the signal delay. Secondly, Cu easily oxidizes, especially at higher temperatures. Further, it is difficult to pattern Cu by means of reactive ion etching (RIE) because, amongst others, a high temperature is required and volatile Cu-compounds have to be found to etch copper.
Nowadays, there a two major ways of fabricating interconnect structures. In the conventional way as a start a conductive layer, i.e. a metal layer, is formed on an insulating layer (or on the substrate) and patterned thereafter usually by means of RIE. When a damascene technology is used, first an insulating layer is deposited and patterned and thereafter the conductive layer is deposited to fill the openings, eventually followed by a planarization step to remove the metal excess. Both ways still require adequate barrier layers to prevent the diffusion of Cu in the insulating layer. The damascene technology has the advantage that the difficult Cu RIE step is avoided. Damascene processing reduces the problem to dry etching of an insulating layer or a stack of insulating layers. The final planarization step yields inlaid horizontal copper interconnect lines in a planar topology. The added bonus of damascene processing is a substantial decrease in the cost factor compared to classical aluminum RIE processing. An expected cost reduction of about 30% has been calculated. The use of plating methods such as electroless and electrolytic copper plating is anticipated to further decrease the cost.
As stated before, due to the difficulty of RIE etching of copper layers, the major processing route for fabricating interconnect structures will be damascene processing, particularly dual damascene processing. This technique allows to build up horizontal metal patterns as well as vertical metal connections in the surrounding insulating layers. These vertical metal connections are required in order to be able to provide a conductive connection between two horizontal metal patterns being processed in different metal levels. To provide such a connection, usually first openings have to be formed in the insulating layer or in the stack of insulating layers between two different metal levels and filled thereafter with a conductive material. Examples of such openings are via holes or contact holes or trenches. To meet the high density integration requirements, the diameter of these openings is continuously decreasing, while at the same time the aspect ratio of these openings is increasing. Due to the small diameter and the high aspect ratios, the creation of these opening, especially the lithographic steps and the dry etchings steps involved, as well as the conformal filling of these openings with a metal or the combination of a metal and a barrier layer poses severe problems.
In patent application U.S. Pat. No. 4873565, incorporated herein by reference, an interconnection between metallization layers of a semiconductor device separated by an insulator is disclosed. A lead is covered with a diffusion barrier layer and a stud is formed above the diffusion barrier layer. Afterwards, the stud is covered with a corrosion preventing material on the sidewalls and on the top surface of the stud. The insulating material is then applied over the conductor and a second metallization level covers the insulating layer. Using this kind of interconnects, problems related to reliability and waste space of the surface area are eliminated. The above mentioned method does not take in account the problem of out-diffusion of copper in the surrounding insulating layer.
In patent application U.S. Pat. No. 4866008, incorporated herein by reference, the authors provide a method of forming a self-aligned conductive pillar on a lower level metallization interconnect to an upper level metallization. This invention focuses on the method by which the conductive pillars are formed by a self-aligned process over the first metallization interconnect with advantages in increased packaging density of structures on the device and a reduced current density in the conductive pillars.